1. Technical Field of the Invention PA1 2. Background Art
This invention relates to correction of soft errors in computer memory by scrubbing. More particularly, it relates to scrub operations which interrupt SDRAM memory STR mode.
Dynamic Random Access Memory (DRAM) chips need to have the charge in their array cells periodically refreshed to retain the data contents. This refresh is normally initiated by commands issued by a memory controller external to the DRAMs. Synchronous DRAMs (SDRAMs) provide a mode, Self-Timed Refresh (STR) mode, during which the SDRAM initiates refresh internally provided no read or write accesses to memory occur. Computer SDRAM memory subsystems utilize less power for STR mode verses externally initiated refresh.
Further to reduce power consumption, SDRAM memory can be put in a self-timed refresh mode during which read or write requests are not allowed. A memory controller would typically wait for an interval of no memory activity (such as, reads or writes) before causing SDRAMs to enter STR mode.
Soft errors in computer memory are often corrected by scrubbing. Scrubbing refers to periodically or otherwise reading data, correcting any correctable errors, and writing the corrected data back to memory.
If scrubbing is suspended when the memory is in self-timed refresh mode, soft errors can accumulate in the memory. If scrubbing is not suspended during self-time refresh (STR) mode, the memory must exit self-timed refresh to execute the scrubbing operation. After the scrubbing operation, if another interval of time is waited and there are no system or I/O read or write requests to memory, unnecessary power is consumed.
It is an object of the invention to provide an improved memory controller.
It is a further object of the invention to provide an improved controller system and method for memory refresh and scrub operations.
It is a further object of the invention to provide for reduced power memory refresh and scrub operations.